Ready to try this for yourself? Here's a more complete version you can start with, that includes stimulus and output.

The code implies this logic diagram.

Use mouse-wheel to zoom, and mouse-drag to pan.

Click an element in the diagram to highlight. The element is highlighted in the code above as well.

Note that signals are carried into stage @4 for printing.

The end of the build log includes output from our code.

Navigating waveforms becomes easier.

  • Highlight the $aa , $bb , and $cc signals with <Ctrl>-click. (They highlight in the other views as well.) Correlate the computed $cc values with the $aa and $bb inputs. (Values are in hexadecimal.)
  • It is easy to correlate a value of $cc with its corresponding $aa and $bb, despite the timing difference, because of the gray invalid signal values. In our code, validity is provided by the $valid signal. Validity also provides additional checking and clock gating logic automatically!
  • Open the "SV" signals (by clicking "+"). This is what you would be debugging when coding SystemVerilog. (Yikes!!!)
  • SandPiper can generate trace files that can be viewed in traditional waveform viewers with similar benefits to the ones in this custom waveform viewer by taking advantage of X's, design hierarchy, pipeline knowledge, and signal and hierarchy names with special characters. Waveforms are easy to correlate with the TL-Verilog source code.

You can edit the model here. Compile/simulate (under the "E" menu). Diagram, waveform, etc. update on successful compilation. (Check the build log.)

Can you update this code to perform a 3-D distance calculation?

dist = sqrt(x^2 + y^2 + z^2)

See what happens in the diagram if you move logic (and printing) to stage @15 .